AEgis Technologies

  • Junior FPGA/ASIC Verification Engineer

    Job Locations US-AL-Huntsville
    # of Openings
  • Overview

    What do you get when you bring together the brightest minds and place them into an exciting, fast-paced environment that fosters intellectual growth and rewards based on impact, not tenure?


    You get one of the best privately held small business headquartered in Huntsville, Alabama, that provides advanced technology and expert consulting services to industries throughout the world. AEgis specializes in modeling & simulation (M&S) and micro/nanoscale technology development. Our core competencies  include simulation software and training simulators; geospatial databases; 3D models; war fighter exercise support; systems engineering and analysis; verification, validation, and accreditation (VV&A); test and evaluation support; Hardware-in-the-Loop (HWIL) and Man-in-the-Loop (MIL) simulation. AEgis' Nanogenesis Division excels in advancing cutting edge micro and nanoscale technologies from concept to deployment with applications ranging from defense to energy to biotechnology.


    AEgis is developing cutting edge products to visualize and integrate defense planning components! Using the best technologies and processes from the commercial sector, we’re bringing new solutions to DoD’s unique problem space.

    The position for Junior FPGA/ASIC Verification Engineer requires the ability to adapt to rapidly evolving problems, customers’ needs, and varying priorities.  The successful candidate will be responsible for independent verification and validation of firmware.  Tasks range from firmware documentation and source code assessment, bus functional model creation, stimulus generation, and regression testing.


    Required Clearance Level: Secret



    Required Education:

    • BS in Computer Science/Engineering and 2-7 years of experience
    • MS in Computer Science/Engineering and 0-5 years of experience

    The Candidate at a minimum should possess:

    • Familiarity with HDL (VHDL, verilog, SystemVerilog) based FPGA design and debugging techniques.
    • Experience using Industry Standard HDL Simulation tools such as Modelsim, Questasim, Incisive, VCS, NCsim, etc
    • Experience with any of the following verification methodologies: UVM, OVM, AVM
    • Experience using SystemVerilog based Testbenches in any of the following areas:

    o  Sequence Based Stimulus
    o  Universal Verification Components (UVCs)
    o  Scoreboards
    o  Testbench Infrastructure

    • Familiarity with Code Coverage and closure techniques
    • Strong analytical, logical and mathematical skills required
    • Good writing and communication skills
    • Experience in an agile development environment
    • Experience with development of automation scripts such as Python, Perl, bash, ksh, Make, etc. helpful
    • Linux software development and/or systems
    • Ability to work, produce, and deliver results independently as well as lead small teams

    The following Preferred Skills are a plus: 

    • Experience in Missile Defense industry
    • Experience with test approaches and technologies
    • Experience with Constrained Random Verification Techniques, System Verilog Assertions, and Functional Coverage
    • Experience with Verification IP such as QVIP, VIPCAT
    • Experience with co-modeling using C/C++ via DPI-C


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